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LTC4359 1 4359f typical a pplica t ion fea t ures descrip t ion ideal diode controller with reverse input protection the lt c ? 4359 is a positive high voltage ideal diode control- ler that drives an external n-channel mosfet to replace a schottky diode. it controls the forward voltage drop across the mosfet to ensure smooth current delivery without oscillation even at light loads. if a power source fails or is shorted, a fast turn-off minimizes reverse cur- rent transients. a shutdown mode is available to reduce the quiescent current to 9a. when used in high current diode applications, the LTC4359 reduces power consumption, heat dissipation, voltage loss and pc board area. with its wide operating voltage range, the ability to withstand reverse input voltage, and high temperature rating, the LTC4359 satisfies the demanding requirements of both automotive and telecom applications. the LTC4359 also easily ors power sources in systems with redundant supplies. 12v, 20a automotive reverse battery protection power dissipation vs load current a pplica t ions n reduces power dissipation by replacing a power schottky diode n wide operating voltage range: 4v to 80v n reverse input protection to C 40v n low 9a shutdown current n low 150a operating current n smooth switchover without oscillation n available in 6-lead (2mm 3mm) dfn and 8-lead msop packages n automotive batter y protection n redundant power supplies n telecom infrastructure n computer systems/servers n solar systems l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 4359 ta01 LTC4359 v ss shdn in source out 47nf 1k gate bsc028n06ns smat70a 70v smaj24a 24v v in 12v v out to load current (a) 0 power dissipation (w) 4 8 6 20 4359 ta01a 2 0 5 10 15 10 schottky diode (sbg2040ct) power saved mosfet (bsc028n06ns)
LTC4359 2 4359f a bsolu t e maxi m u m r a t ings in , source , shdn ................................... C 40 v to 100 v out ( note 3) ................................................ C2v to 100 v in C out .................................................. C 100 v to 100 v in C source ................................................. C1 v to 80 v gate ( note 4) .............. v source C0.3 v to v source +10 v (notes 1, 2) top view v ss shdn in out gate source dcb package 6-lead (2mm 3mm) plastic dfn 4 5 7 6 3 2 1 t jmax = 125c, ja = 64c/w exposed pad (pin 7) pcb v ss connection optional 1 2 3 4 gate source nc in 8 7 6 5 out nc v ss shdn top view ms8 package 8-lead plastic msop t jmax = 125c, ja = 160c/w p in c on f igura t ion o r d er i n f or m a t ion operating ambient temperature range ltc 4 359 c .................................................... 0 to 70 c ltc 4 359 i ................................................. ? 40 to 85 c ltc 4 359 h .............................................. ?4 0 to 125 c storage temperature range ...................... ? 65 to 150 c lead temperature ( soldering , 10 sec ) ms p ackage ...................................................... 30 0 c lead free finish tape and reel (mini) tape and reel part marking* package description temperature range LTC4359cdcb#trmpbf LTC4359cdcb#trpbf lfkf 6-lead (2mm 3mm) plastic dfn 0c to 70c LTC4359idcb#trmpbf LTC4359idcb#trpbf lfkf 6-lead (2mm 3mm) plastic dfn C40c to 85c LTC4359hdcb#trmpbf LTC4359hdcb#trpbf lfkf 6-lead (2mm 3mm) plastic dfn C40c to 125c lead free finish tape and reel part marking* package description temperature range LTC4359cms8#pbf LTC4359cms8#trpbf ltfkd 8-lead plastic msop 0c to 70c LTC4359ims8#pbf LTC4359ims8#trpbf ltfkd 8-lead plastic msop C40c to 85c LTC4359hms8#pbf LTC4359hms8#trpbf ltfkd 8-lead plastic msop C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
LTC4359 3 4359f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2. all currents into pins are positive, all voltages are referenced to v ss unless otherwise specified. symbol parameter conditions min typ max units v in operating supply range l 4 80 v i in in current in = 12v in = out =12v, shdn = 0v in = out =24v, shdn = 0v in = ?40v l l l l 0 150 9 15 C15 200 20 30 C40 a a a a i out out current in = 12v, in regulation in = 12v, ?v sd = ?1v in = out =12v, shdn = 0v in = out =24v, shdn = 0v out = 12v, in = shdn = 0v l l l l l 3 5 120 0.8 0.8 6 7.5 200 3 3 12 a a a a a i source source current in = 12v, ?v sd = ?1v in = source = 12v, shdn = 0v source = C40v l l l 1 C0.4 150 4 C0.8 200 15 C1.5 a a ma ?v gate gate drive (gateCsource) in = 4v, i gate = 0, ?1a in = 8v to 80v; i gate = 0, C1a l l 4.5 10 5.5 12 15 15 v v ?v sd source-drain regulation voltage (in Cout) ?v gate = 2.5v l 20 30 45 mv i gate(up) gate pull-up current gate = in, ?v sd = 0.1v l C6 C10 C14 a i gate(down) gate pull-down current fault condition, ?v gate =5v, ?v sd = ?1v shutdown mode, ?v gate = 5v, ?v sd = 0.7v l l 70 0.6 130 180 ma ma t off gate turn-off delay time ?v sd = 0.1v to ?1v, ?v gate < 2v, c gate = 0pf l 0.3 0.5 s v shdn(th) shdn pin input threshold in = 4v to 80v l 0.6 1.2 2 v v shdn( f lt ) shdn pin float voltage in = 4v to 80v l 0.6 1.75 2.5 v i shdn shdn pin current shdn = 0.5v, LTC4359i, LTC4359c shdn = 0.5v, LTC4359h shdn = ?40v maximum allowable leakage, v in = 4v l l l C1 C0.5 C0.4 C2.6 C2.6 C0.8 100 C5 C5 C1.5 a a ma na v source( th) reverse source threshold for gate off gate = 0v, i gate(down) = 1ma l C0.9 C1.8 C2.7 v the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, in = 12v, source = in, unless otherwise noted. note 3. an internal clamp limits the out pin to a minimum of 100v above v ss . driving this pin with more current than 1ma may damage the device. note 4. an internal clamp limits the gate pin to a minimum of 10v above in or 100v above v ss . driving this pin to voltages beyond the clamp may damage the device. e lec t rical c harac t eris t ics
LTC4359 4 4359f typical p er f or m ance c harac t eris t ics out current vs forward voltage drop source current vs forward voltage drop total negative current vs negative input voltage gate current vs forward voltage drop gate drive vs gate current gate turn-off time vs gate capacitance in current in regulation in current in shutdown source current in shutdown v in (v) 0 i in (a) 100 150 80 4359 g01 50 0 20 40 60 200 v in (v) 0 i in (a) 30 40 80 4359 g02 20 10 0 20 40 60 50 t a = ?40c t a = 25c t a = 85c t a = 125c in = source = out shdn = 0v v source (v) 0 i source (a) 6 8 80 4359 g03 4 2 0 20 40 60 10 t a = ?40c t a = 25c t a = 85c t a = 125c in = source = out shdn = 0v ?v sd (v) ?1 i out (a) 80 120 1 4359 g04 40 0 ?0.5 0 0.5 160 v in = 4v v in = 12v v in = 48v ?v sd (v) ?1 i source (a) 50 0 150 100 1 4359 g05 ?50 ?0.5 0 0.5 200 v source = 4v v source > 12v in = source voltage (v) 0 i in + i source + i shdn (ma) ?1 ?1.5 ?2 ?40 4359 g06 ?0.5 0 ?10 ?20 ?30 in = source= shdn ?v sd (mv) ?50 i gate (a) 10 0 ?10 ?20 150 4359 g07 20 30 40 0 50 100 v in = v source = 12v v gate = v in +2.5v i gate (a) 0 ?v gate (v) 10 ?10 4359 g08 5 0 ?5 ?15 15 in = source v in = 4v v in = 8v v in > 12v c gate (nf) 0 t off (ns) 400 600 8 4359 g09 200 0 2 4 6 10 800 v in = 12v ?v sd = 0.1v ?1v
LTC4359 5 4359f p in func t ions exposed pad ( dcb package only): exposed pad may be left open or connected to v ss . gate: gate drive output. the gate pin pulls high, enhanc- ing the n-channel mosfet when the load current creates more than 30 mv of voltage drop across the mosfet. when the load current is small the gate is actively driven to maintain 30 mv across the mosfet. if reverse current flows, a fast pull-down circuit connects the gate to the source pin within 0.3s, turning off the mosfet. in: voltage sense and supply voltage. in is the anode of the ideal diode. the voltage sensed at this pin is used to control the mosfet gate. nc ( ms package only): no connection. not internally connected. out: drain voltage sense. out is the cathode of the ideal diode and the common output when multiple LTC4359s are configured as an ideal diode- or. it connects either di- rectly or through a 2 k resistor to the drain of the n- channel mosfet. the voltage sensed at this pin is used to control the mosfet gate. shdn : shutdown control input. the LTC4359 can be shut down to a low current mode by pulling the shdn pin below 0.6v. pulling this pin above 2 v or disconnecting it allows an internal 2 a current source to turn the part on. maintain board leakage to less than 100 na for proper operation. the shdn pin can be pulled up to 100 v or down to C 40v with respect to v ss without damage. if shutdown feature is not used, connect shdn to in. source: source connection. source is the return path of the gate fast pull-down. connect this pin as close as possible to the source of the external n-channel mosfet. v ss : supply voltage return and device ground. typical p er f or m ance c harac t eris t ics gate turn-off time vs initial over drive gate turn-off time vs final overdrive load current vs forward voltage drop v initial (v) 0 t pd (ns) 150 200 1 4359 g10 100 50 0 0.5 0.25 0.75 v in = 12v ?v sd = v initial ?1v v final (v) 0 t pd (ns) 1500 ?1 4359 g11 1000 500 0 ?0.5 ?0.25 ?0.75 v in = 12v ?v sd = 45mv v final ?v sd (v) 0 current (a) 10 100 4359 g12 8 2 4 6 0 50 25 75 fdms86101 fdb3632 fds3732
LTC4359 6 4359f b lock diagra m 4359 bd charge pump shutdown ? + ? + fpd comp gate amp 30mv 30mv in 2a source shdn gate q1 ?1.7v out v out v in v ss in + ? + ? ? + negative comp
LTC4359 7 4359f o pera t ion the LTC4359 controls an external n-channel mosfet to form an ideal diode. the gate amplifier ( see block dia- gram) senses across in and out and drives the gate of the mosfet to regulate the forward voltage to 30 mv. as the load current increases, gate is driven higher until a point is reached where the mosfet is fully on. further increases in load current result in a forward drop of r ds(on) ? i load . if the load current is reduced, the gate amplifier drives the mosfet gate lower to maintain a 30 mv drop. if the input voltage is reduced to a point where a forward drop of 30 mv cannot be supported, the gate amplifier drives the mosfet off. in the event of a rapid drop in input voltage, such as an input short circuit fault or negative-going voltage spike, reverse current temporarily flows through the mosfet. this current is provided by any load capacitance and by other supplies or batteries that feed the output in diode- or applications. the fpd comp ( fast pull down comparator) quickly responds to this condition by turning the mosfet off in 300ns, thus minimizing the disturbance to the output bus. the in , source, gate and shdn pins are protected against reverse inputs of up to C40v . the negative comp detects negative input potentials at the source pin and quickly pulls gate to source, turning off the mosfet and isolating the load from the negative input. when pulled low the shdn pin turns off most of the internal circuitry, reducing the quiescent current to 9 a and hold- ing the mosfet off. the shdn pin may be either driven high or left open to enable the LTC4359. if left open, an internal 2 a current source pulls shdn high. in applica- tions where q1 is replaced with back-to-back mosfets, the shdn pin serves as an on/off control for the forward path, as well as enabling the diode function. blocking diodes are commonly placed in series with supply inputs for the purpose of oring redundant power sources and protecting against supply reversal. the LTC4359 replaces diodes in these applications with a mosfet to reduce both the voltage drop and power loss associated with a passive solution. the curve shown on page 1 illus- trates the dramatic improvement in power loss achieved in a practical application. this represents significant savings in board area by greatly reducing power dissipation in the pass device. at low input voltages, the improvement in forward voltage loss is readily appreciated where head- room is tight, as shown in figure 2. the LTC4359 operates from 4 v to 80 v and withstands an absolute maximum range of C40 v to 100 v without damage. in automotive applications the LTC4359 operates through load dump, cold crank and two-battery jumps, and it survives reverse battery connections while also protecting the load. a 12 v/20a ideal diode application is shown in figure 1. several external components are included in addition to the mosfet, q1. ideal diodes, like their non-ideal coun- a pplica t ions i n f or m a t ion terparts, exhibit a behavior known as reverse recovery. in combination with parasitic or intentionally introduced inductances, reverse recovery spikes may be generated by an ideal diode during commutation. d1, d2 and r1 protect against these spikes which might otherwise exceed the LTC4359s C40 v to 100 v survival rating. c out also plays a role in absorbing reverse recovery energy. spikes and protection schemes are discussed in detail in the input short circuit faults section. figure 1. 12v/20a ideal diode with reverse input protection 4359 f01 LTC4359 v ss shdn in source q1 bsc028n06ns c out 47nf r1 1k gate d1 smat70a 70v d2 smaj24a 24v v in 12v v out 12v 20a out
LTC4359 8 4359f a pplica t ions i n f or m a t ion it is important to note that the shdn pin, while disabling the LTC4359 and reducing its current consumption to 9a, does not disconnect the load from the input since q1s body diode is ever-present. a second mosfet is required for load switching applications. mosfet selection all load current passes through an external mosfet, q1. the important characteristics of the mosfet are on- resistance, r ds(on) , the maximum drain-source voltage, bv dss , and the gate threshold voltage v gs(th) . gate drive is compatible with 4.5 v logic-level mosfets over the entire operating range of 4 v to 80v . in applications above 8 v, standard 10 v threshold mosfets may be used. an internal clamp limits the gate drive to 15 v maximum between the gate and source pins. for 24 v and higher applications, an external zener clamp ( d4) must be added between gate and source to not exceed the mosfets v gs(max) during input shorts. the maximum allowable drain- source voltage, bv dss , must be higher than the power supply voltage. if the input is grounded, the full supply voltage will appear across the mosfet. if the input is reversed, and the output is held up by a charged capacitor, battery or power supply, the sum of the input and output voltages will appear across the mosfet and bv dss > out + |v in |. the mosfets on-resistance, r ds(on) , directly affects the forward voltage drop and power dissipation. desired forward voltage drop should be less than that of a diode for reduced power dissipation ; 100 mv is a good starting point. choose a mosfet which has: r ds(on) < forward voltage drop i load the resulting power dissipation is p d = (i load ) 2 ? r ds(on) shutdown mode in shutdown, the LTC4359 pulls gate low to source, turning off the mosfet and reducing its current consump- tion to 9 a. shutdown does not interrupt forward current flow, a path is still present through q1s body diode, as shown in figure 1. a second mosfet is needed to block the forward path; see the section load switching and inrush control. when enabled the LTC4359 operates as an ideal diode. if shutdown is not needed, connect shdn to in. shdn may be driven with a 3.3 v or 5 v logic signal, or with an open drain or collector. to assert shdn low, the pull down must sink at least 5 a at 500mv. to enable the part, shdn must be pulled up to at least 2 v. if shdn is driven with an open drain, open collector or switch contact, an internal pull up current of 2a (1 a minimum) asserts shdn high and enables the LTC4359. if leakage from shdn to ground cannot be maintained at less than 100na, add a pull up resistor to >2 v to assure turn on. the self-driven open circuit voltage is limited internally to 2.5 v. when floating the impedance is high and shdn is subject to capacitive coupling from nearby clock lines or traces exhibiting high dv/dt. bypass shdn to v ss with 10nf to eliminate injection. figure 3 a is the simplest way to control the shutdown pin. since the control signal ground is different from the shdn pin reference, v ss , there could be momentary glitches on shdn during transients. figures 3 b and 3 c are alternative solutions that level shift the control signal and eliminate glitches. figure 2. forward voltage drop comparison between mosfet and schottky diode voltage (v) 0 current (a) 10 15 0.5 4359 f02 5 0 0.2 0.1 0.3 0.4 20 mosfet (bsc028n06ns) schottky diode (sbg2040ct)
LTC4359 9 4359f figure 3a. shdn control figure 3b. transistor shdn control figure 3c. opto-isolator shdn control input short circuit faults the dynamic behavior of an active, ideal diode entering reverse bias is most accurately characterized by a delay followed by a period of reverse recovery. during the delay phase some reverse current is built up, limited by parasitic resistances and inductances. during the reverse recovery phase, energy stored in the parasitic inductances is trans- ferred to other elements in the circuit. current slew rates during reverse recovery may reach 100a/s or higher. high slew rates coupled with parasitic inductances in series with the input and output paths may cause poten- tially destructive transients to appear at the in, source and out pins of the LTC4359 during reverse recovery. a zero impedance short circuit directly across the input and ground is especially troublesome because it permits the highest possible reverse current to build up during the delay phase. when the mosfet finally commutates the reverse current the LTC4359 in and source pins experience a negative voltage spike, while the out pin spikes in the positive direction. to prevent damage to the LTC4359 under conditions of input short circuit, protect the in, source and out pins as shown in figure 4 . the in and source pins are protected by clamping to the v ss pin with two transzorbs or tvs . for input voltages 24 v and greater, d4 is needed to protect the mosfets gate oxide during input short circuit conditions. negative spikes, seen after the mosfet turns off during an input short, are clamped by d2, a 24v tvs . d2 allows reverse inputs to 24 v while keeping the mosfet off and is not required if reverse input protection a pplica t ions i n f or m a t ion figure 4. reverse recovery produces inductive spikes at the in, source and out pins. the polarity of step recovery is shown across parasitic inductances 4359 f04 LTC4359 v ss shdn in source out r1 1k gate q1 fdms86101 reverse recovery current input parasitic inductance + ? d4 ddz9699t 12v v in v out c out 1.5f c load input short output parasitic inductance + ? d1 smat70a 70v d2 smaj24a 24v 4359 f03a LTC4359 1k vn2222ll v ss shdn offon 4359 f03b LTC4359 1k 240k 100k 100k 240k 48v 2n5551 v ss shdn in onoff 2n5401 4359 f03c LTC4359 1k 2m 1m moc 207m 2k 48v v ss shdn in offon
LTC4359 10 4359f is not needed. d1, a 70 v tvs , protects in and source in the positive direction during load steps and overvoltage conditions. out can be protected by an output capacitor, c out of at least 1.5 f, a tvs across the mosfet or by the mosfets avalanche breakdown. care must be taken if the mosfets avalanche breakdown is used to protect the out pin. the mosfets bv dss must be sufficiently lower than 100 v, and the mosfets avalanche energy rat- ing must be ample enough to absorb the inductive energy. if a tvs across the mosfet or the mosfet avalanche is used to protect the out pin, c out can be reduced to 47nf. c out and r1 preserve the fast turn off time when output parasitic inductance causes the in and out volt- ages to drop quickly. paralleling supplies multiple LTC4359s can be used to combine the outputs of two or more supplies for redundancy or for droop sharing, as shown in figure 5. for redundant supplies, the supply with the highest output voltage sources most or all of the load current. if this supplys output is quickly shorted to ground while delivering load current, the flow of current temporarily reverses and flows backwards through the LTC4359s mosfet. the LTC4359 senses this reverse a pplica t ions i n f or m a t ion LTC4359 v ss in d2a smaj24ca 24v out c outa 1.5f c outb 1.5f gate q1a fdms86101 12v 10a bus r1a 1k LTC4359 v ss in source shdn source out gate q1b fdms86101 psa v ina = 12v rtna psb v inb = 12v rtnb d2b smaj24ca 24v 4359 f05 r1b 1k shdn figure 5. redundant power supplies current and activates a fast pull-down to quickly turn off the mosfet. if the other, initially lower, supply was not delivering any load current at the time of the fault, the output falls until the body diode of its oring mosfet conducts. mean-while, the LTC4359 charges the mosfet gate with 10 a until the forward drop is reduced to 30 mv. if this supply was sharing load current at the time of the fault, its associated oring mosfet was already driven partially on. in this case, the LTC4359 will simply drive the mosfet gate harder in an effort to maintain a drop of 30mv. droop sharing can be accomplished if both power supply output voltages and output impedances are nearly equal. the 30 mv regulation technique ensures smooth load sharing between outputs without oscillation. the degree of sharing is a function of mosfet r ds(on) , the output impedance of the supplies and their initial output voltages. load switching and inrush control by adding a second mosfet as shown in figure 6, the LTC4359 can be used to control power flow in the for- ward direction while retaining ideal diode behavior in the reverse direction. the body diodes of q1 and q2 prohibit on off 4359 f06 LTC4359 v ss in out shdn gate source q1 fdms86101 r4 10k c1 10nf v in 28v q2 fqa140n10 r3 10 v out 28v 10a c load c out 1.5f r1 1k d4 ddz9699t 12v d1 smaj58a 58v d2 smaj24a 24v figure 6. 28v load switch and ideal diode with reverse input protection
LTC4359 11 4359f a pplica t ions i n f or m a t ion current flow when the mosfets are off. q1 serves as the ideal diode, while q2 acts as a switch to control forward power flow. on/off control is provided by the shdn pin, and c1 and r2 may be added if inrush control is desired. when shdn is driven high and provided v in > v out + 30mv, gate sources 10 a and gradually charges c1, pulling up both mosfet gates. q2 operates as a source follower and i inrush = 10a ? c load c1 if v in LTC4359 will be activated but holds q1 and q2 off until the input exceeds the output by 30mv. in this way normal diode behavior of the circuit is preserved, but with soft starting when the diode turns on. when shdn is pulled low, gate pulls the mosfet gates down quickly to source turning off both forward and reverse paths, and the input current is reduced to 9a. while c1 and r2 may be omitted if soft starting is not needed, r3 is necessary to prevent mosfet parasitic oscillations and must be placed close to q2. layout considerations connect the in, source and out pins as close as possible to the mosfet source and drain pins. keep the traces to the mosfet wide and short to minimize resistive losses as shown in figure 7. place surge suppressors and necessary transient protection components close to the LTC4359 using short lead lengths. for the dfn package, pin spacing may be a concern at voltages greater than 30 v. check creepage and clearance guidelines to determine if this is an issue. to increase the effective pin spacing between high voltage and ground pins, leave the exposed pad connection open. use no-clean flux to minimize pcb contamination. figures 8 through 18 show typical applications of the LTC4359. figure 7a. layout, dcb6 package figure 7b. layout, ms8 package figure 8. 1.2v diodeCor 4359 f07a s s s g 1 2 3 4 8 7 6 5 d d d d v in out LTC4359 gate in dcb6 4 5 7 6 3 2 1 v out source mosfet LTC4359 s s s g 1 2 3 4 8 7 6 5 d d d d mosfet gate in source out ms8 4359 f07b v in v out LTC4359 v ss in out gate q1a bsc011n03ls ?12v ?12v v out 1.2v 20a r1a 1k source v ina 1.2v c load c outa 47nf LTC4359 v ss in out gate q1b bsc011n03ls 4359 f08 r1b 1k source v inb 1.2v c outb 47nf
LTC4359 12 4359f typical a pplica t ions figure 9. lossless solar panel isolation figure 12. 12v load switch and ideal diode with reverse input protection figure 13. 12v load switch and ideal diode with precise undervoltage lockout figure 10. 48v ideal diode with reverse input protection figure 11. 200v ideal diode 4359 f09 LTC4359 v ss shdn in source out gate q1 si4874dy + 12v battery load shunt regulator 100w solar panel 4359 f10 LTC4359 v ss shdn in source out gate q1 ipb200n25n3g d6 smcj150a 150v r2 2k v in 48v v out 48v 10a c load c out 47nf d1 smat70a 70v d2 mmsz5231b 5.1v d3 bzg03c75 75v d5 s1b d4 ddz9699t 12v 4359 f11 LTC4359 v ss shdn in source out gate q1 fdb28n30 r2 2k 1k es1d 0.47f v in 200v v out 200v 1a c load c out 47nf d1 in759a 12v d2 in751a 5.1v d3 cmz5372b 62v r1 100k d4 ddz9699t 12v 4359 f12 LTC4359 v ss shdn in source out gate q1 bsc028n06ns q2 bsc028n06ns r1 1k v in 12v v out 12v 10a c load c out 47nf d2 smaj24ca 24v d3 s1b r3 10 r4 10k c1 10nf onoff 4359 f13 LTC4359 ltc1540 v ss shdn in source gate out c out 1.5f output q2 bsc028n06ns q1 bsc028n06ns 12v input 2m r1 1k 8.2m uv = 10.8v 1m gnd out 10v ddz9697t d2 smaj24ca 24v + ? v ? in + in ? hyst ref
LTC4359 13 4359f figure 14. 24v ideal diode with reverse input protection figure 15. 48v ideal diode without reverse input protection figure 16. diode-or with selectable power supply feeds and reverse input protection figure 17. overvoltage protector and ideal diode blocks reverse input voltage typical a pplica t ions LTC4359 v ss shdn in source out r1 1k gate smaj58a 58v q1 bsc028n06ns fdd16an08a0 10m 4a output (clamped at 16v) 10 d2 smaj24a 24v d1 smat70a 70v v in 12v 4359 f17 ltc4363 gnd shdn uv ov v cc gate out fb enout f lt sns tmr 0.1f 22f c out 47nf 57.6k 4.99k ?27v to 60v dc survival ?40v to 100v transient survival 4359 f14 LTC4359 v ss shdn in source out gate q1 fdms86101 v in 24v v out 24v 10a c out 1.5f d1 smat70a 70v d2 smaj24a 24v r1 1k d4 ddz9699t 12v 4359 f15 LTC4359 v ss shdn in source out gate q1 fdms86101 v in 48v v out 48v 10a c out 47nf d1 smat70a 70v r1 1k d4 ddz9699t 12v d6 smat70a 70v LTC4359 v ss in outgate q1a fdms86101 d4a ddz9699t 12v v out 28v 10a r1a 1k r1b 1k LTC4359 v ss in source shdn source outgate q1b fdms86101 q2a fqa140n10 d1a smaj58a 58v d2a smaj24a 24v d1b smaj58a 58v d2b smaj24a 24v q2b fqa140n10 v ina 28v v inb 28v c load c outa 1.5f c outb 1.5f 4359 f16 d4b ddz9699t 12v onoff onoff shdn
LTC4359 14 4359f p ackage descrip t ion 3.00 0.10 (2 sides) 2.00 0.10 (2 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (tbd) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 1.35 0.10 (2 sides) 1 3 64 pin 1 bar top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dcb6) dfn 0405 0.25 0.05 0.50 bsc pin 1 notch r0.20 or 0.25 45 chamfer 0.25 0.05 1.35 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.70 0.05 3.55 0.05 package outline 0.50 bsc dcb package 6-lead plastic dfn (2mm 3mm) (reference ltc dwg # 05-08-1715 rev a) dcb package 6-lead plastic dfn (2mm w 3mm) (reference ltc dwg # 05-08-1715 rev a) please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings.
LTC4359 15 4359f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. msop (ms8) 0307 rev f 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ? 0.38 (.009 ? .015) typ 0.1016 0.0508 (.004 .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 ? 6 typ detail ?a? detail ?a? gauge plane 1 2 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev f) p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings.
LTC4359 16 4359f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2012 lt 0512 ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments ltc4352 ideal diode controller with monitor controls n-channel mosfet, 0v to 18v operation ltc4354 negative voltage diode-or controller and monitor controls tw o n-channel mosfets, 1s turn-off, 80v operation ltc4355 positive voltage diode-or controller and monitor controls tw o n-channel mosfets, 0.5s turn-off, 80v operation ltc4357 positive high voltage ideal diode controller controls single n-channel mosfet, 0.5s turn-off, 80v operation ltc4358 5a ideal diode internal n channel mosfet, 9v to 26.5v operation lt4363-1/lt4363-2 high voltage surge stopper stops high voltage surges, 4v to 80v, C60v reverse input protection lt4256-1/lt4256-2 positive high voltage hot swap? controllers active current limiting, supplies from 9v to 80v latch-off and automatic retry option lt4256 positive 48v hot swap controller with open-circuit detect foldback current limiting, open-circuit and overcurrent fault output, up to 80v supply ltc4260 positive high voltage hot swap controller with i 2 c and adc, supplies from 8.5v to 80v ltc4223-1/ltc4223-2 dual supply hot swap controller for advanced mezzanine cards and tca controls 12v main and 3.3v auxiliary supplies figure 18. input diode for supply hold-up on plug-in card 4359 f18 LTC4359 v ss in shdn outgate fdb3632 ddz9699t 12v plug-in card backplane 48v v out1 gnd gnd 1k c holdup 1.5f smat70a 70v source ltc4260 hot swap? controller +

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